Prototipatge ràpid de la capa física d'OFDM : cas HIPERLAN/2 /

Consultable des del TDXTítol obtingut de la portada digitalitzadaAquesta tesi presenta l'aplicació d'una nova metodologia de prototipatge ràpid basada en plataformes per a subsistemes de comunicació, en concret, la part digital de la capa física del protocol sense fils HiperLAN/2. Les principals contribucions d'aquest treball de recerca són: - Formulació i validació d'una metodologia de disseny que transforma directament les especificacions a nivell de sistema a plataformes físiques, mantenint de forma intensiva la verificació heterogènia multinivell. - Exploració i implementació de noves arquitectures hardware per millorar algorismes complexos en la cadena HiperLAN/2, obtenint models sintetitzables per la capa física digital de l'emissor i receptor de l'HiperLAN/2. - Prototipatge de la part digital de la capa física de l'emissor HiperLAN/2 amb una tassa de transmissió de dades de 12MBits/s, en una plataforma adequada per a sistemes WLAN. El propòsit d'aquest prototipatge és demostrar l'alta productivitat de la metodologia que acaba implementant el disseny en plataformes físiques. Aquest treball s'estructura en quatre parts: conceptes fonamentals, metodologia de prototipatge ràpid, disseny de la capa física i prototipatge de l'emissor. Als conceptes fonamentals, es fa una introducció a la modulació OFDM explicant el model de senyal, propietats i avantatges d'aquesta modulació. A continuació, es presenta l'estàndard sense fils HiperLAN/2 que utilitza la modulació OFDM. En concret, es presenten els entorns de treball, la topologia, la capa física, la complexitat del model i tipus de ràfegues de l'estàndard HiperLAN/2. A la metodologia de prototipatge ràpid d'un sistema WLAN, es presenta la metodologia utilitzada pel prototipatge de l'emissor i receptor de la part digital de la capa física de l'HiperLAN/2. A continuació es fa una introducció al prototipatge ràpid, s'exposen els requeriments de les plataformes de prototipatge d'un sistema WLAN, es mostren l'estat de l'art d'entorns i plataformes per a sistemes WLAN i s'expliquen les arquitectures de les FPGAs de Virtex. A continuació, es presenta la metodologia WLAN amb els mètodes de sincronització i els fluxos de disseny que utilitza. En concret, es presenten dos fluxos de disseny diferents, un flux clàssic i l'altre més específic adaptats als sistemes WLAN, els quals ofereixen varies alternatives molt interessants de verificació heterogènia multinivell. Per acabar, es comenten els conceptes d'abstracció funcional, d'ortogonalitat i d'heterogeneïtat de la metodologia. Al disseny de la capa física de l'emissor i receptor es mostren en detall les seves estructures i els seus components computacionals. S'han proposat contribucions significatives pels mòduls de la IFFT/FFT, equalitzador de canal, sincronitzador, interleaver/deinterleaver i Viterbi. Els resultats de síntesis mostren la millora en comparació amb dissenys alternatius actuals. Els models obtinguts de l'emissor i del receptor mostren la seva funcionalitat i les seves prestacions a nivell de sistema. Al prototipatge de l'emissor, es descriuen el canvis aplicats al model de l'emissor per tal de fer el prototipatge en una plataforma específica. Al final, es presenten els resultats obtinguts a través de l'analitzador d'espectres i es fa una estimació del consum de potència de l'emissor que validen el mètode proposat.This thesis presents the application of a new platform-based rapid prototyping methodology to the design of a communications subsystem, specifically the digital part of the physical layer of the HiperLAN/2 wireless protocol. The main contributions of this research work are: - Formulation and validation of a design methodology that directly transforms system level specifications to silicon platforms, while stressing heterogeneous multilevel verification. - Exploration and implementation of new hardware architectures to improve some complex algorithms in the HiperLAN/2 chain, obtaining synthesizable models for the digital part of the physical layer of HiperLAN/2 transmitter and receiver, which were validated in the hardware architecture. - Prototyping of the digital part of the physical layer of the HiperLAN/2 transmitter with a 12Mbits/s data transmission rate in a silicon platform, well-suited for WLAN systems. The aim of this prototype is to show the high productivity of the design methodology that ends into real platforms. This dissertation is structured in four parts: fundamental concepts, rapid prototyping methodology, design of the physical layer, and transmitter prototyping. The fundamental concepts part introduce OFDM modulation, and outlines the signal model as well as its advantages and disadvantages. Next, the standard wireless HiperLAN/2, that uses OFDM modulation, is presented. The working environment, network topology, physical layer, model complexity and burst types are discussed. The chapter on rapid prototyping methodology for a WLAN system describes the design methodology proposed to prototype the transmitter and receiver of the digital part of the physical layer of HiperLAN/2, starting from the WLAN system requirements that lead to the selection of specific prototyping platforms. Current HW implementation capabilities are presented through the architecture of Virtex FPGAs, used as core hardware device. Next, we detail the WLAN system design methodology with the design flow and synchronization methods used. Two design flows are presented, a more general flow and a specific one, adapted to WLAN systems. These design flows detail different powerful options of heterogeneous multilevel verification, that profit from modern concepts of functional abstraction, orthogonality and heterogeneity. The part about physical layer design of transmitter and receiver shows their structures and detail their computational components. Significant contributions have been proposed for IFFT/FFT, channel equalizer, synchronization, interleaver/deinterleaver and Viterbi modules. Synthesis results show their performance quality compared to current alternative designs. The overall results obtained from the transmitter and receiver models show also its global behavior and system level performance. Transmitter prototyping describes changes applied to the transmitter model in order to map it into the specific silicon platform. Out of this complete prototype we extracted data from the spectrum analyzer and of transmitter's power consumption that validate the proposed approach

New matrix methodology for algorithmic transparency in assembly line balancing using a genetic algorithm

© 2022. This manuscript version is made available under the CC-BY-NC-ND 4.0 license https://creativecommons.org/licenses/by-nc-nd/4.0/This article focuses on the Mixed-Model Assembly Line Balancing single-target problem of type 2 with single-sided linear assembly line configurations, which is common in the industrial environment of small and medium-sized enterprises (SMEs). The main objective is to achieve Algorithmic Transparency (AT) when using Genetic Algorithms for the resolution of balancing operation times. This is done by means of a new matrix methodology that requires working with product functionalities instead of product references. The achieved AT makes it easier for process engineers to interpret the obtained solutions using Genetic Algorithms and the factors that influence decisions made by algorithms, thereby helping in the later decision-making process. Additionally, through the proposed new matrix methodology, the computational cost is reduced with respect to the stand-alone use of Genetic Algorithms. The AT produced using the new matrix methodology is validated through its application in an industry-based paradigmatic example.Peer ReviewedPostprint (published version

Detection of Wind Turbine Failures through Cross-Information between Neighbouring Turbines

In this paper, the time variation of signals from several SCADA systems of geographically closed turbines are analysed and compared. When operating correctly, they show a clear pattern of joint variation. However, the presence of a failure in one of the turbines causes the signals from the faulty turbine to decouple from the pattern. From this information, SCADA data is used to determine, firstly, how to derive reference signals describing this pattern and, secondly, to compare the evolution of different turbines with respect to this joint variation. This makes it possible to determine whether the behaviour of the assembly is correct, because they maintain the well-functioning patterns, or whether they are decoupled. The presented strategy is very effective and can provide important support for decision making in turbine maintenance and, in the near future, to improve the classification of signals for training supervised normality models. In addition to being a very effective system, it is a low computational cost strategy, which can add great value to the SCADA data systems present in wind farms.Peer ReviewedObjectius de Desenvolupament Sostenible::7 - Energia Assequible i No Contaminant::7.a - Per a 2030, augmentar la cooperació internacional per tal de facilitar l’accés a la investigació i a les tecnolo­gies energètiques no contaminants, incloses les fonts d’energia renovables, l’eficiència energètica i les tecnologies de combustibles fòssils avançades i menys contaminants, i promoure la inversió en infraestructures energètiques i tecnologies d’energia no contaminantObjectius de Desenvolupament Sostenible::7 - Energia Assequible i No Contaminant::7.b - Per a 2030, ampliar la infraestructura i millorar la tecnologia per tal d’oferir serveis d’energia moderns i sos­tenibles per a tots els països en desenvolupament, en particular els països menys avançats, els petits estats insulars en desenvolupament i els països en desenvolupament sense litoral, d’acord amb els programes de suport respectiusObjectius de Desenvolupament Sostenible::7 - Energia Assequible i No ContaminantPostprint (published version

The High Performance Local Radio Area Network

This paper presents an implementation of a channel equalizer for a wireless OFDM according to the IEEE 802.11a and Hiperlan/2 standard. In order to implement the equalizer, algorithms of low computational complexity have been analyzed. A rapid prototype design flow is presented and applied to the prototyping of these equalizer algorithms in real time on a FPGA platform. A new point of view in the prototyping design flow and the verification process is achieved through the last generation system level design environments for DSPs into FPGAs. These environments, called visual data flows, are ideally suited for modeling DSP systems, since they allow a high level of functional abstraction with different data types and operators. The implemented channel equalizer reaches a high degree of hardware simplicity and efficiency, covering the standard specifications

Double Tensor-Decomposition for SCADA Data Completion in Water Networks

Supervisory Control And Data Acquisition (SCADA) systems currently monitor and collect a huge among of data from all kind of processes. Ideally, they must run without interruption, but in practice, some data may be lost due to a sensor failure or a communication breakdown. When it happens, given the nature of these failures, information is lost in bursts, that is, sets of consecutive samples. When this occurs, it is necessary to fill out the gaps of the historical data with a reliable data completion method. This paper presents an ad hoc method to complete the data lost by a SCADA system in case of long bursts. The data correspond to levels of drinking water tanks of a Water Network company which present fluctuation patterns on a daily and a weekly scale. In this work, a new tensorization process and a novel completion algorithm mainly based on two tensor decompositions are presented. Statistical tests are realised, which consist of applying the data reconstruction algorithms, by deliberately removing bursts of data in verified historical databases, to be able to evaluate the real effectiveness of the tested methods. For this application, the presented approach outperforms the other techniques found in the literature

The smARTS_Museum_V1: An open hardware device for remote monitoring of Cultural Heritage indoor environments

This paper presents an easy-to-use, easy-to-customize, and low cost device for remote monitoring of Cultural Heritage environments such as museums, art galleries, and historical archives. The prototype allows measurements of temperature, relative humidity, and dew point. The chip used is an ESP8266 characterized by on-board Wi-Fi. The hardware design is flexible in order to host extra sensors via I2C bus and easy replacement of microcontroller and sensors in the event of either malfunctions or substitution with newer versions. The device is programmable using the Arduino IDE. The data are sent to an IoT platform that allows real-time visualization, analyses, and download. Tests were performed in laboratory and at the Casa de Convalescencia in Vic (Spain), by monitoring the microenvironment of an exhibition cabinet hosting 18th century ceramics. The results achieved are promising: the open hardware and software approach allows plan further implementations and provides a solid base for device customizations; in terms of technology applied to Cultural Heritage, the implementation of open hardware does not only can lower significantly the costs, but also provides scientifically reliable alternatives to off the shelf technology, as well as enhances end-users capability to develop customized devices that can better address specific needs. Keywords: Sustainable technology, Environment monitoring, Cultural Heritage preventive conservatio

Different Approaches to SCADA Data Completion in Water Networks

This work contributes to the techniques used for SCADA (Supervisory Control and Data Acquisition) system data completion in databases containing historical water sensor signals from a water supplier company. Our approach addresses the data restoration problem in two stages. In the first stage, we treat one-dimensional signals by estimating missing data through the combination of two linear predictor filters, one working forwards and one backwards. In the second stage, the data are tensorized to take advantage of the underlying structures at five minute, one day, and one week intervals. Subsequently, a low-range approximation of the tensor is constructed to correct the first stage of the data restoration. This technique requires an offset compensation to guarantee the continuity of the signal at the two ends of the burst. To check the effectiveness of the proposed method, we performed statistical tests by deleting bursts of known sizes in a complete tensor and contrasting different strategies in terms of their performance. For the type of data used, the results show that the proposed data completion approach outperforms other methods, the difference becoming more evident as the size of the bursts of missing data grows

Rapid prototyping with the visual data environment of an OFDM WLAN system

In this paper a rapid prototyping design flow is presented and applied to a prototype of the base-band physical layer of a Hiperlan/2 WLAN transceiver. This physical layer is a high performance multi-rate system that contains computationally intensive algorithms. A new method for prototyping the design flow and verifying the process is to use the latest generation of system level design environments (visual data flow environment) for DSPs. The System Generator and Matlab/Simulink tools form a visual data flow environment for FPGA allow us to model DSP systems and explore algorithms. This environment also translates designs into hardware implementations that are faithful, synthesizable and efficient, which can be explored and refined in rapid prototyping platforms

Implementation of a Channel Equalizer for OFDM Wireless LANs

This paper presents an implementation of a channel equalizer for a wireless OFDM according to the IEEE 802.11a and Hiperlan/2 standard. In order to implement the equalizer, algorithms of low computational complexity have been analyzed. A rapid prototype design flow is presented and applied to the prototyping of these equalizer algorithms in real time on a FPGA platform. A new point of view in the prototyping design flow and the verification process is achieved through the last generation system level design environments for DSPs into FPGAs. These environments, called visual data flows, are ideally suited for modeling DSP systems, since they allow a high level of functional abstraction with different data types and operators. The implemented channel equalizer reaches a high degree of hardware simplicity and efficiency, covering the standard specifications

Low-cost printed antennas design in the band of 2,4GHz

In this article we present a study and the corresponding implementation of low cost printed antennas in the 2,4GHz band. These antennas work with low cost transceivers that give a FR input/output signal in the band of interest. The work is part of a project in the field of sensor networks using technology such as Zigbee or even simpler and cheaper systems. We have focused our attention on parameters such as the antenna impedance, which is very important for achieving maximum power transfer with the transceiver while avoiding adaptation circuits. We are also interested in avoiding balums. We have analyzed these printed antennas in terms of their efficiency and radiation pattern using electromagnetic simulation software. Two structures have been evaluated and compared. The first is a structure derived from a monopole and slot antenna and the second is a printed patch antenna